ABSTRACT Hot-carrier transistors are a class of devices that leverage the excess kinetic energy of carriers. Unlike regular transistors, which rely on steady-state carrier transport,

hot-carrier transistors modulate carriers to high-energy states, resulting in enhanced device speed and functionality. These characteristics are essential for applications that demand rapid

switching and high-frequency operations, such as advanced telecommunications and cutting-edge computing technologies1,2,3,4,5. However, the traditional mechanisms of hot-carrier generation

are either carrier injection6,7,8,9,10,11 or acceleration12,13, which limit device performance in terms of power consumption and negative differential resistance14,15,16,17.

carriers to achieve a subthreshold swing lower than 1 millivolt per decade beyond the Boltzmann limit and a negative differential resistance with a peak-to-valley current ratio greater than

100 at room temperature. Multi-valued logic with a high inverter gain and reconfigurable logic states are further demonstrated. This work reports a multifunctional hot-emitter transistor

with significant potential for low-power and negative-differential-resistance applications, marking a promising advancement for the post-Moore era. SIMILAR CONTENT BEING VIEWED BY OTHERS A

STEEP SWITCHING WSE2 IMPACT IONIZATION FIELD-EFFECT TRANSISTOR Article Open access 14 October 2022 HIGH DRAIN FIELD IMPACT IONIZATION TRANSISTORS AS IDEAL SWITCHES Article Open access 19

October 2024 HIGH-YIELD PARALLEL FABRICATION OF QUANTUM-DOT MONOLAYER SINGLE-ELECTRON DEVICES DISPLAYING COULOMB STAIRCASE, CONTACTED BY GRAPHENE Article Open access 14 July 2021 MAIN

Transistors can be divided into three groups according to Ng and Sze1,2,3: field-effect transistors, potential-effect transistors and hot-carrier transistors. The first two groups are

represented by the metal–oxide–semiconductor field-effect transistor (MOSFET) and the bipolar junction transistor (BJT), respectively, which have achieved great success in modern integrated

circuits, whereas the third group has advantages in speed and multifunction based on the excess kinetic energy of hot carriers4,5, mainly including the hot-electron transistor (HET) and the

real-space-transfer transistor (RSTT). A HET uses a metal or a semiconductor as the base, and when electrons are injected into the base from the emitter, they become hot and fast because

their energy is higher than those in the base, producing a short base transit time and a high-speed device6,7. Two-dimensional materials such as graphene and molybdenum disulfide (MoS2) have

been used as the base to further reduce the base transit time because of their low atomic thickness, providing a potential terahertz operation, which is promising in the next 6G

technologies8,9,10,11. In contrast, an RSTT uses an electrical field to accelerate carriers, which, when they become hot enough, will transfer from one route to another, resulting in

high-speed operation and a negative differential resistance (NDR)12,13, which is highly needed in various fields such as high-frequency oscillators14,15. HETs and RSTTs provide potential

high performance. However, the mechanisms of the hot-carrier generation are either carrier injection or acceleration, which may limit the device performance and function7,8,9,13. Neither of

these devices can provide an ultralow subthreshold swing less than 60 mV dec−1 beyond the Boltzmann limit, which is highly needed for modern low-power applications16,17. In addition, for an

RSTT, the NDR is limited when the device is fabricated using silicon (Si) and germanium (Ge) technology, which is compatible with mainstream semiconductor production. A novel mechanism of

hot-carrier generation is needed to improve the power consumption and NDR of hot-carrier devices. Mixed-dimensional electronic devices fabricated by combining bulk and low-dimensional

materials can utilize the advantages of different dimensional materials in terms of geometric scale, and electrical and optical performance18,19,20,21, and may combine these advantages to

provide a novel mechanism of hot-carrier generation. For low-dimensional materials such as graphene and carbon nanotubes, carrier mobility is high, which can be used to heat carriers using

an electrical field. Meanwhile, various potential barriers can be formed using different energy-band combinations of bulk and low-dimensional materials, which can be used to emit high-energy

carriers. Here we report a mixed-dimensional hot-emitter transistor (HOET) based on double graphene/germanium Schottky junctions. Using stimulated emission of heated carriers, the

transistor achieves a subthreshold swing lower than 1 mV dec−1 and an NDR with a peak-to-valley current ratio greater than 100 at room temperature. Multi-valued logic applications with a

high inverter gain and reconfigurable logic states are further demonstrated based on these characteristics. DEVICE STRUCTURE AND CHARACTERISTICS The transistor is essentially composed of a

monolayer graphene (Gr) with a gap cut in it and a p-type Ge substrate. Gr contacts Ge through the hafnium dioxide (HfO2) window. The two separated Gr layers were used as the emitter

(emitter-Gr) and the base (base-Gr), and the Ge substrate was used as the collector (Fig. 1a,b). Devices were fabricated using Gr transfer and standard semiconductor processing. The

high-quality monolayer Gr was grown by chemical vapour deposition and transferred onto the Ge substrate22 (Extended Data Fig. 1). The gap in the Gr was fabricated using photolithography with

a gap length from 2 μm to 75 μm (Fig. 1c and Methods). The Gr is separated by the gap as tested by current–voltage (_I_–_V_) measurements (Extended Data Fig. 2). The _I_–_V_ characteristics

of the emitter-Gr/p-Ge junction and the base-Gr/p-Ge junction show an on-to-off current ratio of about 103 at ±3 V, indicating the existence of a Schottky barrier between Gr and Ge

(Extended Data Fig. 3a). The temperature-dependent _I_–_V_ characteristics of the junction indicate a thermionic-emission-dominant mechanism where the Schottky barrier height was determined

to be about 0.38 eV (Extended Data Fig. 3b and Methods). See Extended Data Fig. 3 for more junction characteristics. For the transistor, the relationship of the collector current _I_c and

the base voltage _V_b in the transfer characteristics (_I_c–_V_b) shows an abrupt current change beyond the Boltzmann limit where the subthreshold swing (SS) is below 1 mV dec−1 (Fig. 1d),

whereas the one of _I_c and the collector voltage _V_c in the output characteristics (_I_c–_V_c) shows an NDR with a peak-to-valley current ratio (PVR) around 100 (Fig. 1e). ULTRALOW

SUBTHRESHOLD SWING The SS is a basic parameter to characterize the switching performance of a transistor. A smaller SS is preferred for low-power operation; however, it is usually larger

than 60 mV dec−1 because of the Boltzmann limit23. When the HOET works, the emitter bias _V_e is grounded giving the transistor a common-emitter configuration. When the base bias _V_b

increases, at a critical base bias _V_b-critical, a negative collector current _I_c is observed where the current change is rather abrupt (Figs. 1d and 2a). At room temperature, the abrupt

current change is beyond the Boltzmann limit where the minimum SS is in the range of 0.38–1.52 mV dec−1 as _V_c increases, and the range of the current with an SS less than 60 mV dec−1 is

about 1 to 3 orders of magnitude, which could be further increased (Fig. 2b and Methods). For a current with an SS less than 60 mV dec−1, the average SS is from 0.82 mV dec−1 to 6.1 mV dec−1

and the maximum on-current is from 73.9 μA μm−1 to 165.2 μA μm−1, which is one of the best reported results17,24,25,26,27,28,29,30,31 (Fig. 2c). STIMULATED EMISSION OF HEATED CARRIER

MECHANISM It is noted that holes are the main conduction carriers in the HOET because Gr is p-type (Extended Data Fig. 4), and the abrupt negative _I_c indicates a sudden increase in the

hole current flowing out of the collector, which is neither a normal reverse leakage current of the Gr/Ge junctions nor a forward current of the base-Gr/p-Ge junction. Four phenomena shed

light on the device operation mechanism. First, the transfer characteristics are temperature dependent (Fig. 2d). Different from the tunnelling behaviour, the current changes more abruptly

when the temperature increases. The ultralow SS appears when the temperature is above room temperature, which is the working temperature of most realistic systems. Second, the critical base

bias _V_b-critical when _I_c abruptly changes increases linearly with _V_c, and _V_c − _V_b-critical is about 0.7 V, leading to a forward-biased base-Gr/p-Ge junction (Fig. 2e). Third, at

each bias of _V_c, _V_b-critical increases with increasing gap length _d_gap (5 μm to 75 μm in 5-μm steps; Fig. 2f and Extended Data Fig. 5). Finally, _I_c and _I_e increase abruptly at the

same time (Fig. 2g). These phenomena can be summarized as that initially both the emitter-Gr/p-Ge junction and the base-Gr/p-Ge junction are reverse biased, and when the base bias increases

to a critical value, the base-Gr/p-Ge junction is sufficiently forward biased, so that an exceptional number of holes in the emitter-Gr will suddenly be emitted into the Ge collector, while

holes will enter from the emitter to ensure a continuous current from the emitter to the collector. The higher the temperature, the more obvious the phenomenon, and the shorter the gap, the

smaller the critical base bias. We propose a stimulated emission of heated carrier (SEHC) mechanism to explain these phenomena using a structure illustration (Fig. 2h) and an energy-band

diagram (Fig. 2i) of the device. There are four processes that collectively lead to the ultralow SS. In process A (carrier heating), _V_b and the electric field in the emitter-Gr accelerate

holes there to become heated holes; however, they are not hot enough to overcome the emitter-Gr/Ge potential barrier. In process B (carrier injection), holes are injected from Ge into the

base-Gr to become high-energy holes with the forward bias there. In process C (carrier diffusion), the injected high-energy holes in the base-Gr will overcome the potential barriers induced

by the base-Gr/Ge/emitter-Gr structure by diffusion to arrive at the emitter-Gr. In process D (carrier emission), with a higher energy, these arrived holes will pass their energy to the

heated ones in the emitter-Gr through carrier–carrier scattering (CCS)32, making them the stimulated carriers that will continue to participate in the CCS process, causing a

stimulated-carrier multiplication. These stimulated carriers with high energy will overcome the emitter-Gr/Ge barrier with the reverse bias there, leading to an abrupt hole current

(Methods). The Ge collector current will first increase to a peak abruptly and then decrease when the current of the base-Gr/Ge junction begins to dominate. Compact modelling is used to

further explain the multiplication and emission process (Methods and Extended Data Fig. 6). The SEHC mechanism indicates that even a transistor with a continuous Gr channel can still

generate an ultralow SS, which is validated by our experiments (Extended Data Fig. 7). NEGATIVE DIFFERENTIAL RESISTANCE The NDR effect refers to the characteristic where the current of a

device decreases as the voltage increases, which has been widely used in modern electronics such as amplifiers, microwave generators, high-frequency oscillators and high-speed

digital-to-analogue converters, generally evaluated by the ratio of maximum and minimum currents, that is, the PVR33,34,35,36,37,38,39,40,41. However, when using Si and Ge technologies, the

NDR effect generated by a hot-carrier device is limited where the PVR is no more than three42,43,44,45,46. In the HOET, the output characteristics _I_c–_V_c show an obvious NDR (Figs. 1e and

 3a). When the collector bias _V_c increases, _I_c first increases to a peak value, and then decreases to the reverse currents of the Gr/Ge junctions. The output characteristics are

temperature dependent where the NDR gradually vanishes when the temperature decreases (Fig. 3b), and at each bias of _V_b, the voltage _V_c-peak where _I_c achieves its maximum, decreases as

the gap length _d_gap increases (Fig. 3c and Extended Data Fig. 8). These phenomena are consistent with the SEHC mechanism: in the output characteristics, for each negative bias of _V_b, as

the negative bias of _V_c increases, the hot holes at the emitter-Gr are collected by the collector, leading to a large negative _I_c, gradually reaching the peak current. When _V_c further

increases, the bias of the base-Gr/Ge junction changes from a forward bias to a reverse one, and the carrier-injection process stops, leading to the valley current. It should be noted here

that although an RSTT can also generate an NDR, the characteristics are different. In an RSTT, the NDR shows in the _I_b–_V_b curve where _I_b decreases as _V_b increases because the

carriers are accelerated by _V_b to become hot and are transferred to the collector. In a HOET, _I_b never decreases, no matter how large _V_b is (before the device is damaged), which is

also true even for a transistor with a continuous Gr channel, indicating that carriers cannot be accelerated to become hot enough only by applying _V_b. The peak and valley currents increase

with the base bias _V_b (Fig. 3d), and the PVR is from 90.6 to 24.6 (Fig. 3d). When _V_b is −3 V, the high PVR is due to a small leakage current of the Gr/Ge junction, and the best PVR is

126 (Extended Data Fig. 9). This result is one of the highest values for a device using Gr33,34,35,36,37,38,39,40,41, and is higher than any RSTT using Si and Ge technologies42,43,44,45,46

(Fig. 3e), and is also comparable to the best result of a tunnel device using two-dimensional materials14. MULTI-VALUED LOGIC TECHNOLOGY The multifunctional HOET is promising in various

applications. For example, multi-valued logic (MVL) uses more than two logic states to enable rapid and low-power data processing with high-density integration15, and the HOET can be used to

provide a high inverter gain and reconfigurable logic states for MVL, which has rarely been reported before. A circuit was fabricated using three HOETs (T1–T3) in parallel with a common

emitter, a common collector (Ge substrate) and separated bases 1–3, illustrated by an equivalent circuit and device symbols (Fig. 4a,b). The input and output signals are voltage and current,

respectively43 where the lowest voltage potential corresponds to the input logic ‘0’ and the smallest current (absolute value) corresponds to the output logic ‘0’. To demonstrate a high

inverter gain, one base voltage is used as the input signal (IN, taking _V_b3 as an example), and the collector current _I_c is the output signal (OUT; Fig. 4c). Other voltage biases can be

applied to control the shape of the _I_c curve, such as the position where an abrupt change happens. As _V_b3 changed from 0 V to −12 V, the injected carriers from base 3 first arrived at

the emitter of device T3 leading to an abrupt change of _I_c, followed by another two abrupt changes when the injected carriers arrived at the emitters of devices T2 and T1. The relationship

between _I_c and _V_b3 demonstrates that the circuit can be seen as a quaternary (0, 1, 2, 3) digital logic inverter that has three characteristics. First, the inverter gain _g_m

(transconductance d_I_c/d_V_b3) is high when the logic state changes because of the abruptly changing _I_c, approaching 1 mA μm−1 V−1, which can be used to fabricate a low-power MVL (Fig.

4d). Second, more HOETs can be connected in parallel to achieve quinary or even higher system using a simple structure. Third, the dependence of _I_e on _V_b3 is also the behaviour of a

quaternary inverter, which provides more flexibility for circuit design (Fig. 4e,f). To demonstrate reconfigurable logic states, the output characteristics _I_c–_V_c are investigated. _V_c

is used as the input signal (IN), and the collector current _I_c is the output signal (OUT). _I_c is the sum of the collector currents of the three HOETs. For each collector current, the

position where it achieves the maximum value is controlled by its base bias. Therefore, when different combinations of base biases are applied, the logic states of the output signal are

different, that is, they are reconfigurable, leading to different functions. When the input logic signal is (2, 1, 0), if the output logic signal is (0, 1, 2), the circuit is a ternary

digital logic inverter (Fig. 4g). If the output logic signal is (2, 1, 0), it is a ternary follower (Fig. 4h). If the output logic signal is (0, 2, 1), it can be used to construct an adder

(Fig. 4i). More possibilities can be realized by using different base biases, and more HOETs can be connected in parallel to achieve higher system. CONCLUSION Using the SEHC mechanism based

on mixed-dimensional materials, the HOET provides another member of the hot-carrier transistor family, generating an ultralow SS that is one of the lowest reported values and a PVR in the

NDR effect that is one of the highest for Gr devices. By combining the correct materials and device structure, the HOET can provide a multifunctional and high-performance device with

potential applications in low-power and NDR technologies for the post-Moore era. METHODS PREPARATION OF THE SUBSTRATE A p-type (100) Ge substrate with a resistivity of 1–10 Ω cm was cleaned

by hydrofluoric acid (40 wt%) for 60 s to remove native oxide on the surface. A 30-nm-thick HfO2 insulating layer was deposited on top of the Ge substrate by atomic layer deposition at 200 

°C (precursors, tetrakis (dimethylamido) hafnium (Hf (NMe2)4) and water). The bottom of the Ge substrate was scratched, and Ti/Au (5/50 nm) metallization was performed by electron beam

evaporation to form an ohmic contact. Electrode metallization using Ti/Au (5/50 nm) on the surface was formed by photolithography and electron beam evaporation. For photolithography,

photoresist s-1813 (spin-coated at 3,000 rpm for 30 s, baked at 120 °C for 2 min) and LOR3A (spin-coated at 3,000 rpm for 50 s, baked at 190 °C for 5 min) were used in sequence. The HfO2

layer on the substrate was then patterned by photolithography and reactive ion etching (CF4 50 standard cubic centimetres per minute (sccm), 5.0 Pa, radiofrequency power 100 W, 5.5 min),

followed by dilute hydrofluoric acid (5 wt%) etching for 30 s to form a window to the Ge. PREPARATION OF THE MONOLAYER GR FILM Monolayer Gr film was synthesized by chemical vapour deposition

on a commercial copper foil (99.9%, 25-μm thick). The copper foil was first annealed at 1,000 °C under a 5-sccm hydrogen flow and then exposed to a mixture of hydrogen (5 sccm) and methane

(60 sccm) at a total pressure of 100 Pa for 30 min to grow Gr, followed by slow cooling to room temperature. GR FILM TRANSFER AND DEVICE FABRICATION Gr was transferred by using the typical

wet polymethyl methacrylate (PMMA) method. The solution of PMMA (950 kDa molecular weight, Sigma, 4 wt% in ethyl lactate) was first spin-coated on the graphene/Cu foil at 2,000 rpm for 60 s

and cured at 180 °C for 15 min. After removing the Cu foil by chemical etching, the PMMA/Gr film was carefully collected on the desired target substrate and baked. PMMA was then removed by

immersing in acetone at 50 °C to complete the transfer. Finally, the transferred Gr was patterned by photolithography and oxygen plasma etching (200 W, 180 sccm, 2 min). THE EMISSION PROCESS

IN THE SEHC MECHANISM When the collector current increases abruptly, (A) the electric field in the emitter-Gr heats the holes there while (B) high-energy holes are injected from Ge into the

base-Gr, which will arrive at the emitter-Gr by (C) diffusion. Only one injected hole is shown (Extended Data Fig. 6a). The arrived high-energy holes will pass their energy to the heated

ones through (D1) CCS32 (Extended Data Fig. 6b). When the stimulated holes in the emitter-Gr gain enough energy from the injected holes, (D2) a multiplication process happens (Extended Data

Fig. 6c), before the stimulated holes with enough energy are (D3) emitted into Ge with the reverse bias there, leading to the abrupt current (Extended Data Fig. 6d). In the CCS process,

after one collision between carriers, the number of carriers that can cross the Gr/Ge barrier will double, and the energy these carriers possess after the collision is still higher than the

Gr/Ge barrier. In addition, the lateral electric field generated by _V_b can increase these carriers’ energy. Therefore, the carriers after the collision can continue to participate in the

CCS, causing the number of carriers that can cross the barrier to double again. Meanwhile, In the energy domain, the CCS will result in a high-energy-band tail in the energy distribution

function, indicating an increase in high-energy carrier distribution32. Therefore, the continuous CCS process can cause the number of high-energy carriers in the emitter-Gr to increase

repeatedly, leading to a surge in the reverse current. It should be noted that the impact ionization47 cannot be responsible for this phenomenon, as that _I_c never increases abruptly no

matter how large _V_b and the corresponding electric field is applied (before the device is damaged) in the emitter-Gr if the base-Gr/Ge junction is not forward biased. MODELLING OF THE CCS

MULTIPLICATION PROCESS The base bias _V_b determines the current _I_c not only by providing a lateral electric field in the emitter-Gr but also by controlling the injected carriers at the

base-Gr/Ge junction, leading to a complex relationship among the scattering, the multiplication and _V_b, and therefore a complex one between _I_c and _V_b. In fact, multiplication processes

are usually modelled using an experience-based approach47 and we provide an empirical model for the multiplication process in the HOET below. The critical base bias _V_b-critical, where

_I_c increases abruptly, increases linearly with the collector bias _V_c (Fig. 2e) and the gap length _d_gap (Fig. 2f). On the basis of these experimental results, _I_c is described as _I_c 

= _M_ × _I_rev + _I_0, _M_ = _A_/(1 − (_V_b − _V_c)/(_V_b-critical − _V_c)), _V_b-critical = _Bd_gap + _V_c + _C_, where _I_rev is the reverse current of the emitter-Gr/Ge junction before

the CCS multiplication, _M_ is the CCS multiplication factor and _I_0, _A_, _B_ and _C_ are fitting constants. As shown in Extended Data Fig. 6e, the model fits the experimental results

well. MODELLING OF THE GR/GE JUNCTION On the basis of the thermionic-emission current model of a Schottky junction, the Gr/p-Ge Schottky potential barrier height _qϕ_B, ideality factor _η_,

interface state density _D_it and series resistance _R_s are estimated as follows. The relationship of the forward current _I_F of the Gr/Ge junction and temperature _T_ is ln(_I_F/_T_2) = 

_C_ − _q_(_ϕ_B – _V_c/_η_)/_k_ × (1/_T_), where _C_ is a constant, _q_ is the elementary charge, _V_c is the forward voltage bias and _k_ is Boltzmann’s constant3. Using an Arrhenius plot,

the slopes of the fitted lines –_q_(_ϕ_B – _V_c/_η_)/1,000_k_ is plotted against _V_c (Extended Data Fig. 3c), and the _y_ intercept at 0 V is _S_0 = −_qϕ_B/1,000_k_ leading to a _qϕ_B of

about 0.38 eV, while the slope is Slope* = _q_/1,000_kη_ leading to an _η_ of about 1.29. _D_it is estimated using _η_ and _ϕ_B based on a relationship of _η_ = 1 + (_δ_/_ε_0)(_ε_s/_W_d + 

_q_2_D_it), where _δ_ is the thickness of an interfacial layer between Gr and Ge, _ε_0 is the permittivity in vacuum (8.85 × 10−14 F cm−1), _ε_s is the relative dielectric constant (16.2) of

Ge and _W_d is the thickness of the depletion layer of Ge (ref. 3). _W_d = (2_ε_s/_qN_a × (_ψ_bi − _V_c − _kT_/_q_))0.5 where _N_a is the doping concentration of Ge (1016 cm−3) and _ψ_bi is

the built-in potential barrier height in the semiconductor as _ψ_bi = _ϕ_B − _ϕ__n_. _ϕ_n = _kT_/_q_ × ln(_N_v/_N_a) where _N_v is the effective states density of the valence band of Ge

(5.7 × 1018 cm−3). On the basis of these models, _D_it is estimated to be about 2.6 × 1012 cm−2 eV−1. A series resistance _R_s of the junction of about 3 kΩ is extracted by a linear fitting

of the forward _I_–_V_ characteristic at a high voltage bias (Extended Data Fig. 3d). CHARACTERIZATION Characterization of the graphene film and the devices was performed using a confocal

Raman spectrometer (Jobin Yvon Lab RAM HR800), an optical microscope (Nikon LV100ND), a scanning electron microscope (FEI XL30 SFEG using an accelerating voltage of 10 kV) and an atomic

force microscope (Bruker Dimension Icon AFM). The transistors were measured using a semiconductor analyser (Agilent B1500A with a capacitance measurement unit B1500A-A20) and a probe station

(Cascade Microtech 150-PK-PROMOTION) at room temperature, and a vacuum probe station (Lake Shore TTPX/TSM1D1001) at low temperature. For device uniformity, taking the device with a 3-μm gap

as an example, 20 devices were fabricated on a wafer. The transfer characteristics (_V_c = −2 V) show that for SS, sample size = 20, mean = 0.60 mV dec−1 and standard deviation = 0.29 mV 

dec−1, whereas the output characteristics (_V_b = −4 V) show that for PVR, sample size = 20, mean = 15.80 and standard deviation = 2.84. The uniformity can be improved by advanced processes,

such as using a Gr-on-Ge wafer where the Gr is grown directly on Ge instead of manual Gr transfer48. OPPORTUNITIES AND CHALLENGES The SEHC mechanism can be applied to devices composed of

different materials. For example, using a carbon nanotube film/n-Ge junction, n-type HOETs can be fabricated (Extended Data Fig. 10). Complex circuits can be realized by using both the

n-type and p-type HOETs. However, for the HOET to ultimately become practical, a series of problems must be solved including increasing the range of the current with an SS less than 60 mV 

dec−1, improving the PVR in the NDR applications and reducing the hysteresis in the characteristics. At present, although the on-current of the transistor is high, the off-current is also

high, resulting in a limited current range with a SS less than 60 mV dec−1, which is not an intrinsic result of the SEHC mechanism. The off-current should be reduced and the on-current

increased to improve the on-to-off current ratio. To reduce the off-current, (1) the quality of the Gr/semiconductor interface should be improved by using a Gr-on-Ge wafer where the Gr is

grown directly on Ge instead of being transferred48 and (2) other material combinations can be used, such as Gr combined with wider-bandgap semiconductors, where the potential barrier height

of the Gr/semiconductor junction is higher and the intrinsic carrier concentration in the semiconductor is lower. To increase the on-current, the energy of the carriers injected from the

base-Gr should be further increased, perhaps by using asymmetric potential barriers of the base/substrate and emitter/substrate junctions, which can be achieved by using different substrate

semiconductor materials under the base-Gr and the emitter-Gr. These requirements are also necessary for improving the PVR in the NDR applications. Typical transfer and output characteristics

show that the width of the hysteresis window is about 0.25 V and 0.23 V, respectively. However, it should be noted that the hysteresis is not caused by the SEHC mechanism intrinsically, but

by the limited quality of the Gr/Ge interface. Because of the contamination and imperfection during the transfer and fabrication process, the Gr/Ge junction itself shows a large hysteresis.

This can be reduced by using a Gr-on-Ge wafer where the Gr is grown directly on Ge instead of being transferred or by using an encapsulation. DATA AVAILABILITY Relevant data are available

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references ACKNOWLEDGEMENTS This work was supported by National Natural Science Foundation of China (grant numbers 62074150, 62125406, 52272051 and T2293703), Excellent Youth Foundation of

Liaoning (2023JH3/10200003) and National Key Research and Development Program of China (2021YFA1200013). We thank P. Thrower, B. Song, Y.-P. Wang, C. Liu and Z. Han for discussions. AUTHOR

INFORMATION Author notes * These authors contributed equally: Chi Liu, Xin-Zhe Wang, Cong Shen, Lai-Peng Ma AUTHORS AND AFFILIATIONS * Shenyang National Laboratory for Materials Science,

Institute of Metal Research, Chinese Academy of Sciences, Shenyang, China Chi Liu, Xin-Zhe Wang, Lai-Peng Ma, Xu-Qi Yang, Yue Kong, Wei Ma, Yan Liang, Shun Feng, Xiao-Yue Wang, Yu-Ning Wei, 

Xi Zhu, Bo Li, Chang-Ze Li, Shi-Chao Dong, Wen-Cai Ren, Dong-Ming Sun & Hui-Ming Cheng * School of Materials Science and Engineering, University of Science and Technology of China,

Shenyang, China Chi Liu, Xin-Zhe Wang, Lai-Peng Ma, Xu-Qi Yang, Yue Kong, Wei Ma, Yan Liang, Shun Feng, Xiao-Yue Wang, Yu-Ning Wei, Xi Zhu, Bo Li, Chang-Ze Li, Shi-Chao Dong, Wen-Cai Ren, 

Dong-Ming Sun & Hui-Ming Cheng * School of Electronic and Computer Engineering, Peking University, Shenzhen, China Cong Shen & Li-Ning Zhang * Institute of Technology for Carbon

Neutrality, Shenzhen Institute of Advanced Technology, Chinese Academy of Sciences, Shenzhen, People’s Republic of China Hui-Ming Cheng Authors * Chi Liu View author publications You can

also search for this author inPubMed Google Scholar * Xin-Zhe Wang View author publications You can also search for this author inPubMed Google Scholar * Cong Shen View author publications

You can also search for this author inPubMed Google Scholar * Lai-Peng Ma View author publications You can also search for this author inPubMed Google Scholar * Xu-Qi Yang View author

publications You can also search for this author inPubMed Google Scholar * Yue Kong View author publications You can also search for this author inPubMed Google Scholar * Wei Ma View author

publications You can also search for this author inPubMed Google Scholar * Yan Liang View author publications You can also search for this author inPubMed Google Scholar * Shun Feng View

author publications You can also search for this author inPubMed Google Scholar * Xiao-Yue Wang View author publications You can also search for this author inPubMed Google Scholar * Yu-Ning

Wei View author publications You can also search for this author inPubMed Google Scholar * Xi Zhu View author publications You can also search for this author inPubMed Google Scholar * Bo

Li View author publications You can also search for this author inPubMed Google Scholar * Chang-Ze Li View author publications You can also search for this author inPubMed Google Scholar *

Shi-Chao Dong View author publications You can also search for this author inPubMed Google Scholar * Li-Ning Zhang View author publications You can also search for this author inPubMed 

Google Scholar * Wen-Cai Ren View author publications You can also search for this author inPubMed Google Scholar * Dong-Ming Sun View author publications You can also search for this author

inPubMed Google Scholar * Hui-Ming Cheng View author publications You can also search for this author inPubMed Google Scholar CONTRIBUTIONS C.L., D.-M.S. and H.-M.C. conceived the project.

C.L., X.-Z.W., C.S. and L.-P.M. were equal major contributors to this work. C.L. designed the device and the circuit and analysed the data. C.L., X.-Z.W., X.-Q.Y. and Y.K. performed the

experiments as well as electrical measurements assisted by Y.L., S.F., Y.-N.W., X.Z., X.-Y.W., B.L. and C.-Z.L. L.-P.M., W.M. and S.-C.D. carried out graphene growth, transfer and

characterization supervised by W.-C.R. C.L., C.S. and L.-N.Z. proposed the device mechanism. C.S. performed the device modelling supervised by L.-N.Z. C.L. and D.-M.S. wrote the paper. All

authors discussed the results and commented on the paper. CORRESPONDING AUTHORS Correspondence to Chi Liu, Li-Ning Zhang or Dong-Ming Sun. ETHICS DECLARATIONS COMPETING INTERESTS The authors

declare no competing interests. PEER REVIEW PEER REVIEW INFORMATION _Nature_ thanks Filippo Giannazzo and Carsten Strobel for their contribution to the peer review of this work. ADDITIONAL

INFORMATION PUBLISHER’S NOTE Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations. EXTENDED DATA FIGURES AND TABLES EXTENDED

DATA FIG. 1 CHARACTERIZATION OF THE MONOLAYER GRAPHENE FILM. A Raman spectra of 10 randomly selected points on the graphene film transferred onto the SiO2/Si substrate. The characteristic

peaks observed at about 1590 cm−1 (G band) and about 2680 cm−1 (2D band) with the I2D > IG and the absence of defect-induced D band (1350 cm−1) indicate that the film is a high-quality

monolayer graphene. B Large-area HRTEM image of the graphene film (scale bar: 5 nm). The well-defined hexagonal lattice in the absence of defects and impurities confirms the high-quality of

the monolayer graphene film. EXTENDED DATA FIG. 2 _I_−_V_ CHARACTERISTICS OF TRANSISTORS WITH BIASES OF _V_B = 0 AND _V_C = _V_E. The devices use A a graphene channel with a gap and B a

continuous graphene channel. When there is a gap in the graphene channel, the limited _I_e indicates the separation of the emitter-Gr and the base-Gr. On the other hand, when a continuous

graphene channel is used, the large currents (_I_e = _I_b) are the currents in the continuous graphene channel. EXTENDED DATA FIG. 3 _I_−_V_ CHARACTERISTICS OF THE GR/P-GE JUNCTIONS. A The

rectifying current ratio of about 103 at ±3 V indicates the existence of a Schottky potential barrier between graphene and Ge at room temperature. Gr was grounded and _V_c was applied on the

Ge substrate. B _I_−_V_ characteristics of the Gr-Ge junction measured at various temperatures from 224 K. C Arrhenius plots with _V_c from 0.084 to 0.18 V in steps of 0.012 V. Inset: The

fitted slope plotted against _V_c, where the y-intercept at 0 V (_S_0) and the slope (Slope*) gives a Schottky potential barrier height _q__ϕ__B_ of 0.38 eV and an ideality factor _η_ of

1.29 (Methods). D A series resistance of the junction of about 3 kΩ is extracted by linear fitting of the forward _I_−_V_ characteristics when _V_c is much larger than the built-in potential

barrier height _ψ_bi. EXTENDED DATA FIG. 4 INVESTIGATION OF THE CARRIER TYPE IN THE GRAPHENE CHANNEL. A Correlation between the frequencies of G and 2D Raman bands of the graphene on Ge,

showing a typical p-type doping without a significant strain caused by processing. 130 Raman spectra were collected for the statistical analysis of doping and strain. B Electrical methods

were used to further clarify the doping type. Input characteristics _I_b−_V_b of a transistor with a continuous graphene channel was investigated. When the base bias _V_b is less than −1 V,

a collector bias _V_c from −1 to −9 V leads to reverse biased emitter-Gr/Ge and base-Gr/Ge junctions. Therefore, the large _I_b is the conduction current in the continuous graphene channel.

When _V_c increases, _I_b also increases. This can be explained by C the corresponding energy band diagram of the Gr/Ge junction with an increasing collector bias _V_c. When _V_c increases,

because of the quantum capacitance effect of Gr, its Fermi-energy level will go down as shown using the blue arrow in the diagram. Only if the graphene is p-type so that the conduction

carriers are holes, will the carrier concentration increase and lead to an increasing current. Therefore, in the HOET, the conduction carriers are holes. EXTENDED DATA FIG. 5 TRANSFER

CHARACTERISTICS _I_C−_V_B OF HOETS. The length of gap _d_gap between emitter-Gr and base-Gr increases from A 5 to O 75 μm. For each bias of _V_c, the critical base bias when the collector

current _I_c starts to increase abruptly tends to increase with _d_gap. EXTENDED DATA FIG. 6 ILLUSTRATIONS FOR THE EMISSION PROCESS IN THE STIMULATED EMISSION OF HEATED CARRIER MECHANISM. A

When the collector current increases abruptly, (A) the electric field in the emitter-Gr heats the holes there while (B) high-energy holes are injected from Ge into the base-Gr which will

arrive at the emitter-Gr by (C) diffusion. B The arrived high-energy holes will pass their energy to the heated ones through (D1) carrier-carrier scattering (CCS). C After the stimulated

holes in the emitter-Gr have enough energy from the injected holes, (D2) a multiplication process happens, before D the stimulated holes with enough energy are (D3) emitted into Ge with the

reverse bias there, leading to the abrupt current. E The empirical model fits the experimental results well for the multiplication process in the HOET. EXTENDED DATA FIG. 7 ILLUSTRATIONS AND

_I_−_V_ CHARACTERISTICS OF A TRANSISTOR WITH A CONTINUOUS GRAPHENE (GR) CHANNEL. A Illustration of the device structure. B Energy band diagram near the Gr channel in (a). The stimulated

emission of heated carrier (SEHC) mechanism indicates that even a transistor with a continuous Gr channel can generate an ultra-low SS. At a critical base bias, the left part of Gr/Ge

junction will remain reverse biased while the right one will become forward biased. Four similar processes cause the ultra-low SS: A (carrier heating), B (carrier injection), C (carrier

diffusion) where the injected high-energy holes will arrive at the left part of Gr by diffusion either using a path in Gr or one passing through Ge, D (carrier emission). C Transfer

characteristics _I_c−_V_b show a negative abruptly changing collector current _I_c. D Output characteristics _I_c−_V_c show an obvious negative differential resistance. EXTENDED DATA FIG. 8

OUTPUT CHARACTERISTICS _I_C−_V_C OF HOETS. The length of gap _d_gap between emitter-Gr and base-Gr increases from A 5 to O 75 μm. For each bias of _V_b, the voltage where _I_c achieves its

maximum tends to decrease as _d_gap increases. EXTENDED DATA FIG. 9 AN OUTPUT CHARACTERISTIC _I_C−_V_C OF A TRANSISTOR WITH A 35-ΜM GAP AT _V_B = −3 V. The peak to valley current ratio (PVR)

is 126, higher than any Gr device and Si/Ge RSTT, and is comparable to the best two-dimensional tunnel device. EXTENDED DATA FIG. 10 _I_−_V_ CHARACTERISTICS OF AN N-TYPE HOET FABRICATED

BASED ON CNT FILM/N-GE JUNCTIONS. A 4-μm gap in the CNT film channel was formed using photolithography. A Transfer characteristics _I_c−_V_b show an abruptly changing collector current _I_c.

Note that since electrons are the conduction carrier, the polarity of the bias is opposite to that of the p-type device. B Output characteristics _I_c−_V_c show an obvious negative

differential resistance. The peak-to-valley current ratio (PVR) is higher than 18. RIGHTS AND PERMISSIONS OPEN ACCESS This article is licensed under a Creative Commons Attribution 4.0

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http://creativecommons.org/licenses/by/4.0/. Reprints and permissions ABOUT THIS ARTICLE CITE THIS ARTICLE Liu, C., Wang, XZ., Shen, C. _et al._ A hot-emitter transistor based on stimulated

emission of heated carriers. _Nature_ 632, 782–787 (2024). https://doi.org/10.1038/s41586-024-07785-3 Download citation * Received: 05 September 2023 * Accepted: 04 July 2024 * Published: 14

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