ABSTRACT III-V semiconductors have been intensively studied with the goal of realizing metal-oxide-semiconductor field-effect transistors (MOSFETs) with high mobility, a high on-off ratio,

and low power consumption as next-generation transistors designed to replace current Si technology. Of these semiconductors, a narrow band-gap semiconductor InAs has strong Rashba spin-orbit

interaction, thus making it advantageous in terms of both high field-effect transistor (FET) performance and efficient spin control. Here we report a high-performance InAs nanowire MOSFET

with a gate-all-around (GAA) structure, where we simultaneously control the spin precession using the Rashba interaction. Our FET has a high on-off ratio (104~106) and a high field-effect

one order of magnitude smaller than those of back-gated nanowire MOSFETs. Our demonstration of high FET performance and spin controllability offers a new way of realizing low-power

consumption nanoscale spin MOSFETs. SIMILAR CONTENT BEING VIEWED BY OTHERS SPIN-STATES IN MOS2 THIN-FILM TRANSISTORS DISTINGUISHED BY OPERANDO ELECTRON SPIN RESONANCE Article Open access 05

March 2021 DOMAIN WALL ENABLED STEEP SLOPE SWITCHING IN MOS2 TRANSISTORS TOWARDS HYSTERESIS-FREE OPERATION Article Open access 01 November 2022 NON-VOLATILE ELECTRIC CONTROL OF SPIN-ORBIT

TORQUES IN AN OXIDE TWO-DIMENSIONAL ELECTRON GAS Article Open access 05 May 2023 INTRODUCTION The high electron mobility of III-V semiconductors makes them good candidates for the

development of field-effect transistors that can be operated with high speed, a high on-off ratio, and a low power consumption. Of these semiconductors, those showing band structures with

large spin-orbit splitting have been independently attracting great interest in relation to spin FET applications1. The large band splitting is mostly associated with the Rashba spin-orbit

interaction (SOI) generated with an electric field induced by structural inversion asymmetry. The Rashba SOI is given by the Hamiltonian, _H_ = _e_α0 ∙ (σ × _k_), where _e_ is an elementary

charge, α0 is a Rashba coefficient determined from the band structure of a bulk material, σ is the Pauli matrix, _k_ is the electron wave vector and _E_ is the electric field vector2,3,4.

The Rashba coupling parameter given by α ≡ α0 _eE_ is an important index as a measure of modulating electron spin, and increasing and controlling α with the gate voltage has been a focus of

attention. To obtain better electric-field control of the Rashba SOI, III-V semiconductors such as GaAs/AlGaAs, GaInAs/InP, InAs, InSb and InGaAs have been investigated for various

structures including two-dimensional electron gas (2DEG) in heterostructures5,6,7, quantum wells (QW)8,9,10 and quantum wires11 using a top-down microfabrication process. These studies

reported that Rashba parameters range from α = 0.3 × 10−11 to 1 × 10−11 eVm (refs 6,7,8,9,10,11) and have a gate voltage _V_ g tunability of ~1.4 × 10−12 eVm/V (refs 5,6,7,8,9). On the other

hand, InAs nanowires with surface electron confinement potential in a sub-micron width have been examined mostly in the form of conventional bottom- or top-gated devices12,13,14,15,16. They

have shown a larger α (1 × 10−11–3 × 10−11 eVm) but the _V_ g tunability was as small as that of former reports using a top-down approach7,8,9,10,11 within a gate voltage range of 0–20 V.

Recently, Liang _et al_.17 reported ion-gated InAs nanowire device, exhibiting _V_ g tunable efficiency more than ten times higher than previously reported13, 14, 16, 18. This marked

progress in efficiency brought about low-gate voltage operation leading to low-power consumption. However, since ion-gated device requires very long response time, a prototype device

employing standard MOS design that excels in operation speed is critically needed. Here, we report high gate-tunability of the Rashba SOI in an InAs nanowire MOSFET employing gate-all-around

(GAA) geometry19, in which gate-induced electric field is more enhanced and more uniform than those in conventional bottom- or top-gated nanowire devices13,14,15,16, multigated nanowires18,

and Ω-shape (partially coaxial) gated devices20,21,22. The Rashba parameter that we obtained by weak antilocalization measurements is 0.6 × 10−11–2 × 10−11 eVm, and the gate voltage

tunability is 1.2 × 10−11–2.4 × 10−11 eVm/V, the latter being ten times larger than that obtained for various types of III-V semiconductors including InAs nanowire

MOSFETs6,7,8,9,10,11,12,13,14,15,16. This is also comparable to the best _V_ g tunability achieved for an ion-gated InAs nanowire FET17. In addition to the excellent _V_ g tunability of the

Rashba SOI, our device exhibits excellent FET characteristics including a high on-off ratio (104~106) and a high field-effect mobility (1200 cm2/Vs). As MOSFETs have faster responses than

ion-gated devices, which normally require considerable time for electric double layer stabilization23, our demonstration of both the excellent FET performance and high tunability of the

Rashba SOI in a small _V_ g range could lead to the development of a practical spin nanowire MOSFET with low power consumption that is compatible with the currently used Si transistor

platform. RESULTS Figure 1(a) is a schematic illustration of our GAA InAs nanowire FET, which we fabricated using a similar method to the one we used for our previous nanowire FETs24, 25.

GAA geometry, which is also called surrounding gate26 or wrap-gate27 geometry, has been used not only to induce a uniform electric field but also to suppress the short-channel effect of

transistors28 with an improvement in nanowire FET performance29, 30. To obtain a high carrier density and thus induce a strong electric field, we used the high-κ gate dielectrics of

Al2O3/HfO2 (2 nm/4 nm) grown by atomic layer deposition (ALD). The InAs nanowire coated with the above dielectrics was deposited on a pre-patterned substrate and then gate metal was

evaporated onto the nanowire. This two-stage deposition of gate metal allows us to fabricate a GAA structure. As shown in Fig. 1(b), our sample is covered by the gate electrode over 90% of

the channel length, which allows us to ignore the contributions of the ungated regions (for details see Method). Figure 1(c) shows a TEM image of a cross-section of a typical nanowire FET.

We find that layered gate dielectrics and GAA geometry are formed according to our MOSFET design. These structures are also examined with energy dispersive X-ray spectrometry (EDS). The

false colour images in Fig. 1(d–i) rule out any significant migration or diffusion of the deposited elements or contamination during the device processing along the entire channel. We first

describe FET operation at various temperatures. Figure 2(a) shows the transfer characteristics of the device measured at room temperature for different source drain voltages _V_ sd of 100 to

500 mV. As shown in the inset, the subthreshold slope (SS) and on-off ratio are 350 mV/dec and over 104 at room temperature (RT). Here SS is defined as _dV_ g/_d_log_I_ sd with the

source-drain current _I_ sd. While the SS values for our typical devices fabricated in the same manner usually exceed 200 mV/dec at RT, which is larger than the ideal RT limit of 60 mV/dec,

the on-off ratio exhibits good performance and is generally higher than ~104. When we decrease the measurement temperature to 1.5 K, the SS and on-off ratio are greatly improved to 25 mV/dec

and 106, respectively, as shown in Fig. 2(c). The high on-off ratio at RT and 1.5 K are comparable to the excellent previously reported values for GAA InAs nanowires24, 25, 31,32,33 and GAA

InGaAs nanowires34. Moreover, steep increase in _I_ sd within _V_ g~1 V indicates that our GAA device is operated at lower voltage than conventional back-gated nanowire FETs with

cylinder-on-plane (COP) geometry13,14,15,16. Figure 2(b,d) show the output characteristics for various _V_ g values measured at RT and 1.5 K, showing that a good saturation is obtained

within a _V_ sd of 0.5 V. To investigate how robust our FET is under ambient conditions, we compare the same device in different measurement runs. Figure 3(a) compares the device transfer

characteristics measured before the first cooling with those measured after 6 months, during which time the sample was stored in ambient air when not in use. Although reduction in _I_ sd is

accompanied by a reduction in the on-off ratio from 2 × 104 to 1 × 104, we observe no notable change in SS values between the two cases. Moreover, our GAA device shows robust and clear

transfer characteristics for various temperatures down to 1.5 K [Fig. 3(b)] after 6 months interval. We note that the data shown in Fig. 2(a–d) were measured after several cooling cycles,

indicating that our FET performs well even after being affected by thermal cycles and the ambient conditions. We next compare the field-effect mobility μ for the two cases and examine the

temperature dependence. μ is given by \(\frac{{{L}_{g}}^{2}}{C}\frac{d}{d{V}_{g}}(\frac{{I}_{sd}}{{V}_{sd}})\), where _L_ g is a gate length of 3.3 μm, _C_ is a gate capacitance of 2.29 × 

10−14 F, and _V_ sd is the source-drain bias. The sample exposed to the first thermal cycle shows mobilities of 1000 cm2/Vs at RT and 1200 cm2/Vs at 1.5 K, as shown in Fig. 3(c). Our device

shows less _T_ dependence than other InAs nanowire GAA devices32, 33. Indeed, many of our GAA devices possess mobilities of 1000–1500 cm2/Vs at room temperature. The value is one order of

magnitude higher than that of a previously reported InAs GAA device using the gate dielectrics of HfO2 (~109 cm2/Vs)31, and comparable to single-crystalline and pure-phase InAs nanowire with

GAA geometry33 (1500 cm2/Vs) and high-mobility InGaAs nanowire FETs (1030 cm2/Vs)34. However, after several thermal cycles and long-time storage under ambient conditions, the mobility

decreased to around 400 cm2/Vs, which is nevertheless higher than the mobility of a high-κ gated MoS2 2D transistor35 or a Si nanowire FET36. The decreased mobility may be attributed to

increase in access resistance resulting from the nanowire segment that is not coated by the gate metal, possibly due to impurities adhered to that segment by repeated thermal cycles or

during sample storage. Therefore, the decrease is merely in the extrinsic mobility, not the intrinsic one. This is also supported by the fact that SS after 6 months, which shows linear

temperature dependence that is characteristic to standard FETs [Fig. 3(d)], has no notable difference from SS for the first cooling from room temperature to 1.5 K, indicating that surface

states of the nanowire under the gate electrode are expected to be unaffected. In this paper, we use data obtained for the sample when it had a field effect mobility of ~400 cm2/Vs unless

otherwise stated. However, we emphasize that gate efficiency on the nanowire channel was not degraded during 6 months, as is seen from virtually unchanged SS values. This is also consistent

with the results obtained by magnetotransport measurements as we discuss later, in which we confirm that the gate controllability of the Rashba parameter was not degraded after 6 months.

Having examined the FET performance of our device, we then investigated the effects of a spin-orbit interaction by conducting magnetotransport measurements at 1.5 K. Figure 4(a) shows the

correction of magnetoconductance (ΔG ≡ Δ_G_(B) − Δ_G_(0)) as a function of a magnetic field (_B_), where the magnetoconductance was deduced from the two-terminal dc-transport at _V_ sd = 10 

mV. The data have been smoothed over _V_ g ± 15 mV and _B_ ± 15 mT to exclude universal conductance fluctuations or other random fluctuations caused by impurities, as in refs 14, 16. In

addition, our data are further averaged with respect to the reversed magnetic field sweep direction to fit the data with better accuracy as described below. As _V_ g increases, _B_

dependence of Δ_G_ changes from a dip to a peak, indicating a crossover from weak localization to weak antilocalization37, 38, which occurs for conducting channels in a variety of materials

and devices9, 39, 40 in the presence of a strong spin-orbit interaction. Such a crossover from weak localization to weak antilocalization has also been observed for various types of InAs

FETs12,13,14,15,16,17, where spin-orbit interaction is considered to be the Rashba SOI originating from a strong electric field. These devices have a mean free path shorter than the nanowire

diameter, indicating that an electrical channel in a nanowire can be reasonably analysed in the framework of the disordered one-dimensional weak antilocalization model reported in ref. 38,

$${\rm{\Delta }}G=-\frac{2{e}^{2}}{h{L}_{g}}[\frac{3}{2}{(\frac{1}{{l}_{\varphi }^{2}}+\frac{4}{3{l}_{so}^{2}}+\frac{1}{D{\tau }_{B}})}^{-1/2}-\frac{1}{2}{(\frac{1}{{l}_{\varphi

}^{2}}+\frac{1}{D{\tau }_{B}})}^{-1/2}]$$ (1) where _h_ is Planck constant, _L_ g is the gate length, _l_ ϕ is the phase coherence length, _l_ so is the spin-orbit relaxation length, _D_ is

the diffusion constant, and τB is the magnetic relaxation time. Here τB is given by $${\tau }_{B}=\frac{3{{l}_{B}}^{4}}{{W}^{2}D}$$ (2) with _l_ B being the magnetic length given by

\({l}_{B}=\sqrt{h/(2\pi eB)}\). Note that using this relation reduces fitting parameters to only _l_ so and _l_ ϕ. Our device has a typical mean free path of 12 nm, which is smaller than the

nanowire diameter of 100 nm. Therefore, the use of Eq. (1) is justified, as plotted by the solid lines in Fig. 4(a), which fit well with our data. _l_ so and _l_ ϕ are shown in Fig. 4(b),

together with τso and τϕ, which are deduced from τso(τϕ) = _l_ so(_l_ ϕ)2/_D_ with diffusion constant _D_ given by _D_ = vF 2 τ/3. Here _v_ F is the Fermi velocity and τ is the momentum

scattering time given by τ = μ_m_ */_e_ (_m_ *: effective electron mass) with _m_ * = 0.023 _m_ e (_m_ e: electron mass). We also note that _l_ ϕ > _W_, which is required for a

one-dimensional weak antilocalization condition, is satisfied as shown in Fig. 4(b). As _V_ g increases, _l_ so decreases and _l_ ϕ increases, reaching a crossover at _V_ g ~ 0.5 V. This

corresponds to the gate voltage at which a crossover from weak localization to weak antilocalization occurs. The decreasing _l_ so accompanied by a rapid decrease in τso demonstrates that

the spin-orbit relaxation length is tuned significantly by the electric field induced by the gate voltage. DISCUSSION We in turn compare the _V_ g tunability of _l_ so obtained for our

device with those already reported for other InAs nanowire FETs13,14,15,16,17,18. As is clearly seen in Fig. 5(a), where _l_ so is plotted against _V_ g, our GAA MOS-type device shows

superior _V_ g tunability; _l_ so is modulated several times in a _V_ g range an order of magnitude smaller than that used to operate back or top-gated (cylinder-on-plane) InAs

nanowires13,14,15,16, 18, indicating that our GAA MOSFET can offer much lower power consumption than conventional nanowire MOSFETs. The tunability for our device also reaches a high level

comparable to the previously reported best controllability obtained for an InAs nanowire device operated with electrolyte gating17. It is noteworthy that such high _V_ g tunability is

achieved for a MOSFET, which has an advantage of easier and faster operation than ion-gated devices particularly in temperature-variable measurements. This is because ion-gated devices

typically require the temperature to be increased to change the carrier density for ion polarization41, which itself requires a long time to stabilize23. These types of devices sometimes

take more than ten hours for temperature variation to minimize sample electrochemical degrading42. Using experimentally extracted _l_ so, we calculated the Rashba coupling parameter αR and

corresponding electric field _E_ R. Here αR is given by \({\alpha }_{R}=\frac{{\hslash }^{2}}{2{m}^{\ast }{l}_{so}}={\alpha }_{0}e{E}_{R}\), where _ħ_ is the reduced Planck constant and α0

is the Rashba coefficient of bulk InAs α0 = 1.17 nm2 (ref. 43). Figure 5(b) shows αR and _E_ R as a function of _V_ g. The red and blue circles indicate data obtained for the first cooling

[with a mobility of 1200 cm2/Vs, as shown in Fig. 3(a,c and d)] and for the cooling carried out with an interval of 6 months [with a mobility of 400 cm2/Vs, as shown in Fig. 3(a–d)]. Despite

the long time interval and difference in mobility, the αR and _E_ R values obtained from two measurements are in good agreement. When _V_ g is increased above the threshold voltage _V_ th,

αR and _E_ R increase linearly as expected. A rapid increase in αR up to _V_ g ~ 1.5 V provides Rashba parameter tunability reaching 1.2 × 10−11 eVm/V. Figure 5(b) also summarizes the _V_ g

tunability of the Rashba SOI extracted from various devices, where our device is compared with an ion-gated InAs nanowire device17, a back-gated cylinder-on-plane InAs nanowire13, and other

two-dimensional FETs fabricated from strong SOI material7, 8. Here αR is estimated by analysing the crossover from weak localization to weak anti-localization for the nanowire devices, and

is extracted from beating patterns in magnetotransport for the two-dimensional FETs. While the _V_ g tunabilities of αR and _E_ R for our sample are about a quarter of their counterparts for

the ion-gated device17, they greatly exceed the values obtained for a conventional back-gated cylinder-on-plane InAs nanowire MOSFET13 as well as those obtained for two-dimensional FETs

fabricated from III-V material7, 8. We further investigate the ratio of the calculated electric field _E_ L expected from GAA geometry and the _E_ R value that is directly associated with

the Rashba SOI. In the cylinder capacitance model, the charge line density _Q_ L and associated electric field _E_ L are given by, $${Q}_{L}=\frac{C({V}_{g}-{V}_{fb})}{{L}_{g}}$$ (3)

$${E}_{L}=\frac{{Q}_{L}}{\pi ({\varepsilon }_{0}{\varepsilon }_{InAs})W}$$ (4) where _C_ is the cylindrical gate capacitance (see Method), _V_ fb is the gate voltage that gives flat band

condition, _W_ is the nanowire diameter, and ε0 and εInAs are the vacuum and relative permittivities. The slope of the _V_ g dependence of _E_ L is extracted for our device from these

equations. We use _C_ = 2.29 × 10−14 F, _L_ g = 3.3 μm, _W_ = 100 nm for our sample. As for _V_ fb. we use gate voltage given by the intercept of _E_ R = 0 for the Rashba measurements. The

dash-dotted line in Fig. 5(b) tracing our data has a slope that is twenty times smaller than that for calculated _E_ L. We then consider the ion-gated device described in ref. 17, where the

authors adapted the same cylinder capacitance model to their device. We calculate _E_ L using the corresponding values shown in Supplementary Information in ref. 17 (_C_ = 1.44 × 10−14 F,

_L_ g = 2 μm, _W_ = 25 nm). Their data are also traced by the dashed line with a slope twenty times smaller than _E_ L calculated for their device. The inconsistency between _E_ L and _E_ R

is pointed out in ref. 17, and they attributed it to electric field decay due to screening by the gate-induced charge in the nanowire channel44, also noting that this decay would appear

similarly in GAA MOS-type nanowires. We consider that the inconsistency we found with our device is partly associated with this charge screening, which is mainly due to surface-state

pinning15. We also mention that the field gradient on _V_ g can be reduced by trap states or interface states possibly incorporated in a gate insulator, which would act as a reservoir for

gate-induced carriers45, 46, even though our device is expected to have less interface state density due to the insertion of an Al2O3 layer before HfO2 growth47. When we assume the presence

of interface states located between the InAs surface and the Al2O3 gate insulator, the interface state density required to explain the dash-dotted line would be very large, reaching ~3 × 

1014 eV−1cm−2 based on a model similar to that described in ref. 45. This unreasonably large value of the interface-state density itself suggests that our device is significantly affected by

the charge screening effect. To highlight the efficiency of our device, we compare _E_ L, _E_ R and _E_ R/_E_ L between the two devices. As expected from the device geometry, _E_ L for _V_

g–_V_ fb of 1 V is calculated to be 4.0 × 108 V/m for an ion-gated device (with their assumption of a Debye length of 1 nm (ref. 22), which corresponds to the gate insulator thickness in GAA

geometry) and 1.0 × 108 V/m for our device. It should be noted that, while we compare devices with different nanowire diameters, _E_ L is determined solely by the gate insulator material

and gate geometry, and is thus inherently nearly independent of nanowire width. Although _E_ L for our device is about one quarter of its electrolyte counterpart, it is significant that a

MOSFET has such a high _E_ L value owing to its thin high-κ gate dielectrics. When _E_ R is plotted as a function of _E_ L, instead of _V_ g, as shown in Fig. 5(c), data from our MOS device

and those from the ion-gated device fall on almost the same line. This consistency between totally different devices highlights the fact that our GAA device is fabricated as well as an

ion-gated device as regards the gate-control efficiency that affects the Rashba SOI. Although the _E_ R to _E_ L ratio decreases to about 5% for both devices, our MOS device does not require

any thermal cycle for gate voltage change unlike ion-gated device, and therefore enables _in-situ_ continuous tuning of αR. Furthermore, the _E_ R to _E_ L ratio in our device is nearly

independent of _V_ g [see Fig. 5(d)], thus ensuring more stable SOI operation by sweeping gate voltage. The above results demonstrate that our GAA geometry with high-κ gate dielectrics has

the Rashba SOI tuning efficiency close to the best value ever achieved, at the same time as enabling the continuous _in-situ_ tuning due to the faster response of MOS design. We believe that

these advantages will make our device a prototype nanoscale MOSFET for use in realizing practical spin control application. METHOD InAs nanowires are grown by vapour-liquid-solid method

using gold nanoparticles as catalysts48. For the gate dielectrics, we combined two high-κ gate dielectrics of Al2O3 (2 nm) and HfO2 (4 nm) grown by ALD. The growth of Al2O3 before HfO2 can

improve the interface between InAs and gate dielectrics, which may reduce the interface state density in ALD-grown gate dielectrics47. As shown in Fig. 1(b), more than 90% of the channel

length of our device is coated with a gate electrode. When we considered the contributions of ungated regions and deduced the corrected mobility as in refs 33 and 34, we found that the

corrected mobility differs less than 5%, which allows us to disregard the contributions of the ungated regions. The sample was measured with a standard DC transport method or ac lock-in

techniques at room temperature down to 1.5 K using a cryostat. To obtain the gate capacitance, we used a standard cylindrical model. When a gate insulator with a thickness of _h_ coats a

nanowire with a radius _r_ and length _L_ g, the gate capacitance _C_ is given by \(C=\frac{2\pi {\varepsilon }_{0}{\varepsilon }_{h}{L}_{g}}{\mathrm{ln}(1+\frac{h}{r})}\), where εh is

relative permittivity of the gate insulator. Since our device employed a double layer of high-κ gate dielectrics, Al2O3 and HfO2, we use the total gate capacitance _C_ tot given by

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AUTHOR INFORMATION AUTHORS AND AFFILIATIONS * NTT Basic Research Laboratories, NTT Corporation, 3-1 Morinosato-Wakamiya, Atsugi, Kanagawa, 243-0198, Japan K. Takase, Y. Ashikawa, G. Zhang, 

K. Tateno & S. Sasaki * Department of Physics, Tohoku University, 6-3 Aramaki Aza Aoba, Aoba-ku, Sendai, 980-8578, Japan Y. Ashikawa & S. Sasaki Authors * K. Takase View author

publications You can also search for this author inPubMed Google Scholar * Y. Ashikawa View author publications You can also search for this author inPubMed Google Scholar * G. Zhang View

author publications You can also search for this author inPubMed Google Scholar * K. Tateno View author publications You can also search for this author inPubMed Google Scholar * S. Sasaki

View author publications You can also search for this author inPubMed Google Scholar CONTRIBUTIONS K.Takase and S.S. conceived the experiments. K.Takase and Y.A. measured and analyzed the

data. Y.A. fabricated the devices under the supervision of S.S. K.Tateno and G.Z. grew InAs nanowires. K.Takase wrote the manuscript with input from all the authors. CORRESPONDING AUTHOR

Correspondence to K. Takase. ETHICS DECLARATIONS COMPETING INTERESTS The authors declare that they have no competing interests. ADDITIONAL INFORMATION PUBLISHER'S NOTE: Springer Nature

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http://creativecommons.org/licenses/by/4.0/. Reprints and permissions ABOUT THIS ARTICLE CITE THIS ARTICLE Takase, K., Ashikawa, Y., Zhang, G. _et al._ Highly gate-tuneable Rashba spin-orbit

interaction in a gate-all-around InAs nanowire metal-oxide-semiconductor field-effect transistor. _Sci Rep_ 7, 930 (2017). https://doi.org/10.1038/s41598-017-01080-0 Download citation *

Received: 16 November 2016 * Accepted: 27 March 2017 * Published: 19 April 2017 * DOI: https://doi.org/10.1038/s41598-017-01080-0 SHARE THIS ARTICLE Anyone you share the following link with

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